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Logic Circuits Designs

Introduction | Logic Circuit Design Process | Build and Test | Universal Gates | Programmable Logic Devices | Study Tools | Practice Quiz

 

Introduction

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Last week, we discussed the process of using truth tables and SOP representations to describe the behavior of a desired digital circuit. This week, we continue on this topic and describe how to refine and implement designs. We will see how more efficient designs are possible, even after simplification, by using the concept of universal gates - in our case this refers to NAND gate logic. We also discuss the use of programmable logic in implementing logic circuits.

 

Logic Circuit Design Process

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The process for designing a digital circuit was illustrated last week. The steps required to design a simple combinational logic circuit are:

  1. Create a truth table for your logic circuit, describing how you want your output(s) to respond to their inputs.
  2. Create the SOP expression from your truth table, making sure that all input conditions generating logic 1's out are part of this expression.
  3. Simplify the SOP expression via Boolean reduction or a software program.
  4. Draw logic circuits for each product term, including any inverters and all inputs to the AND gates to create the different products.
  5. Add an OR gate to the final logic circuit drawing to allow the summing to occur.
  6. Simulate the circuit.
  7. Build and test the final circuit.

As an illustration of using these steps (except the final step that requires a lab), consider the design of a simple majority tester. This is a circuit with three inputs that outputs a 1 whenever at least two of the inputs are 1. This circuit has practical applications where multiple instruments are used for redundancy in determining which inputs are correct (majority rules).

STEP 1 - CREATE TRUTH TABLE

A

B

C

X

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

1

1

0

0

0

1

0

1

1

1

1

0

1

1

1

1

1

STEP 2 - CREATE SOP EXPRESSION

The SOP for this truth table is:

STEP 3 - SIMPLIFY THE SOP EXPRESSION

Using either Boolean rules or software, the SOP expression can be simplified to:

STEPS 4 AND 5 - DRAW PRODUCT TERMS AND SUM TOGETHER

Circuit for Steps 4 & 5: Draw Product Terms and Sum Together

This circuit is drawn in the Multisim application and shows three inputs, labeled A, B and C going into a circuit that consists of 5 two-input gates, in three stages, with an output labeled “X”. 
Stage 1:  A and B are the inputs to the first two-input AND gate labeled “74LS08D/U1A” .  B and C are the inputs to the second two-input AND gate labeled “74LS08D/U1B” .   A and C are the inputs to the third two-input AND gate labeled “74LS08D/U1C” . 
Stage 2:  The output of the first two-input AND gate, with A and B inputs, is labeled “74LS08D/U1A” and is the first input to a two-input OR gate labeled “74LS32D/U2A”.  The output of the second two-input AND gate, with B and C inputs, is labeled “74LS08D/U1B”and is the second input to the same two-input OR gate labeled “74LS32D/U2A”.  The output of this two-input OR gate, is the first input into the final, stage 3 two-input OR gate.
Stage 3:  The output of the second stage two-input OR gate is the first input to the final two-input OR gate labeled “74LS32D/U2B”.  The output of the third two-input AND gate, with A and C inputs, is labeled “74LS08D/U1C”is the second input to the final two-input OR gate labeled “74LS32D/U2B”.  The output of this final stage 3 two-input OR gate is the output of the circuit and is labeled “X”.

Image Description

STEP 6 - SIMULATE THE CIRCUIT

Adding switches for the input and a logic probe for the output allows a full simulation. One of the conditions is shown below:

Circuit for Step 6: Simulate the Circuit

This circuit described above is drawn again in the Multisim application with several additions.  In this version, the circuit has added switches to control the inputs, has been grounded, and has power added.  The final output is now connected to an LED labeled “X” that is shown in RED to indicate that it is “ON” and it is marked at 2.5 V. 
A, B and C inputs are connected to switches showing both an off and on position and marked Key=A, Key =B, and Key =C respectively to indicate the keyboard key used to toggle the individual switch in the Multisim application. (For instance, the A key on the keyboard would be used to toggle the switch for the A input between the open to the closed positions.) 
One side of each of the switches for A, B and C inputs is connected to the power source labeled “Vcc” , and marked at 5 volts.  The other side of each switch for the A, B and C inputs is connected to the Ground, denoted by a triangle with the vortex pointing down.
The final output is now connected to an LED labeled “X” that is shown using a ¼ inch RED circular dot with six ¼ inch red line “rays” coming out  from the dot to indicate that the LED  is “ON”.  The voltage marking at this point of the circuit shows 2.5 V. 

Image Description

In performing the simulation, ensure that the circuit operates correctly for all possible input combinations.

 

Build and Test

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The final step in the digital design process that we laid out above requires us to build and test the circuit we have drawn. This means, again, that we have to learn several things before building the circuit and being able to test it to prove that it works. Once we have learned these few things and have built a working circuit, we will have learned and applied a lot of information!

Here is a list of some things we need to know before we build and test any circuit:

 

Universal Gates

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An interesting property of both NAND and NOR gates is that they each can be used to produce all of the logic functions. For example, tying both inputs of a NAND gate together produces an inverter. Using the NAND inverter on the output of a regular NAND gate creates an AND gate equivalent; using the NAND inverter on each input to a NAND gate creates an OR gate equivalent. You can verify these operations with simple truth tables.

There are several reasons that the universal property of NAND gates is critical. Digital logic integrated circuits are created using transistor switches to determine whether the IC voltage input (Vcc) or IC ground input is output based on the state of the inputs. In designing these ICs, NAND gates require fewer transistors than any other type of gate. This means less power used by an individual gate and a higher density of more complex circuits.

A second reason to use a simple type of gate is to minimize the number of different types of ICs required for a design. Multiple different types of ICs require a large inventory of circuit maintenance. This second reason is not as important thanks to the rise of programmable logic.

The MultiSim Logic Converter is designed to allow conversion to a NAND-gate design. Returning to the majority tester design, note the final button on the Logic Converter:

MultiSim Logic Converter

This picture shows a screenshot of the Logic Converter from within the MultiSim application.   The information listed in the Logic Converter refers back to the Majority Tester that was mentioned prior in the lecture. 
The top ribbon of the Logic Converter is marked “Logic Converter – XLC1” on the left hand side and has the X button to close the screen on the right had side. 
The left had portion of the logic converter screen shows the truth table and is a large white rectangle divided into three sections.  The buttons for inputs A, B and C are selected on top of the rectangle using white circular dots.  The buttons for inputs D through H are deselected on top of the rectangle using grey circular dots.  The truth table area is divided into three white rectangles, the left rectangle has the rows labeled 000 through 007 for the 8 entries in the truth table.  The center white rectangle has the truth table inputs for the majority tester:
Row 000:  A=0, B=0, C=0
Row 001:  A=0, B=0, C=1
Row 002:  A=0, B=1, C=0
Row 003:  A=0, B=1, C=1
Row 004:  A=1, B=0, C=0
Row 005:  A=1, B=0, C=1
Row 006:  A=1, B=1, C=0
Row 007:  A=1, B=1, C=1
The right white rectangle has the outputs of the truth table:
Row 000:  X=0
Row 001:  X=0
Row 002:  X=0
Row 003:  X=1
Row 004:  X=0
Row 005:  X=1
Row 006:  X=1
Row 007:  X=1
The right portion of the logic converter screen uses rectangular grey boxes to show the six  “conversion” options available for the logic converter within the Multisim application. 
The first option shows the option to go from a circuit schematic to the truth table, and is marked on the left side with a small two input OR gate, a center black arrow pointing from the left to the right, and on the right with one line of a truth table showing inputs of 1 and 0, and an output of 1.
The second option shows the option to go from the truth table to an equivalent Boolean equation, and is marked on the left side with one line of a truth table showing inputs of 1 and 0, and an output of 1, a center black arrow pointing from the left to the right, and on the right side by the letters “A|B”.
The third option shows the option to go from the truth table to an equivalent SIMPLIFIED Boolean equation, and is marked on the left side with one line of a truth table showing inputs of 1 and 0, and an output of 1, a center black arrow pointing from the left to the right, and on the right side by the letters “A|B”.  The letters “SIMP” are marked on top of the center black arrow.
The fourth option shows the option to go from an equivalent Boolean equation to a truth table, and is marked on the left side by the letters “A|B”, a center black arrow pointing from the left to the right, and on the right side by one line of a truth table showing inputs of 1 and 0, and an output of 1.
The fifth option shows the option to go from an equivalent Boolean equation to a circuit schematic, and is marked on the left side by the letters “A|B”, a center black arrow pointing from the left to the right, and on the right side with a small two input OR gate.
The sixth option shows the option to go from an equivalent Boolean equation to a NAND gate only solution, and is marked on the left side by the letters “A|B”, a center black arrow pointing from the left to the right, and on the right side by the letters “NAND”.
The bottom ribbon of the Logic Converter is a white long rectangle that shows the Boolean expression for the circuit and is marked “AC + AB + BC”. 

Image Description

Pressing this button converts the design to one using only NAND gates:

MultiSim Circuit Schematic

This picture shows a screenshot of a four-stage circuit schematic created from within the MultiSim application for the majority tester circuit shown in the logic converter screen above using ONLY two-input NAND gates.  Inputs A, B and C are shown in the top left of the diagram denoted using white 1/16 inch circles.  Input A delivery is marked with a red “1”, input B delivery is marked with a red “3” and input C delivery is marked with a red “2”.
 
Stage 1:  A and C are the inputs to the first two-input NAND gate, with the output of this gate marked by a red “4”.  A and B are the inputs to the second two-input NAND gate, with the output of this gate marked by a red “5”.   B and C are the inputs to the third two-input NAND gate with the output of this gate marked by a red “8”.    
 
Stage 2:  The output of the first two two-input NAND gates, with A/B and A/C inputs marked with the red “4” and “5” lead to another two-input NAND gate.  The output for this two-input NAND gate is marked with a red “6”.  The output of this two-input OR gate, is the first input into the stage 3 two-input NAND gate.
 
Stage 3:  The output of the second stage two-input NAND gate marked with a red “6” is used as the input into BOTH inputs on the two-input NAND gate in stage 3.  The output of this two-input NAND gate, is the first input into the stage 4 two-input NAND gate, and is marked with a red “7”.
 
Stage 4:  .  The output of the stage 3 two-input NAND gate, is the first input into the stage 4 two-input NAND gate, and is marked with a red “7”.  The output of the stage 1 two-input NAND gate with B and C inputs, and marked by a red “8”, is the second input to the final two-input NAND gate.    The output of this final stage 4 two-input NAND gate is the output of the circuit.

Image Description

At first glance, this seems less efficient than the design using AND-OR gates, six gates instead of five. However, this uses only one type of IC instead of two. In more complicated designs, the use of NAND logic will usually require fewer total gates as well.

 

Programmable Logic Devices

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Programmable logic devices (PLD) allow the user to define the logic function that the IC will perform and the pins that will be used as inputs and outputs. Most of these devices can be re-programmed to perform different logic functions. Some of these devices can be programmed only once, which stops them from being RE-programmable. Programmable devices are available in different sizes (number of gates) and technology (in-circuit programmable, not re-programmable, out of circuit programmable, CMOS, TTL-compatible outputs, and so on).

The most important aspect of these devices is that they can perform different logic functions using different input/output pin assignments during their lifespan. A 5-input OR gate can be re-programmed to become an 8-input NAND gate, using different (OR some of the same) input and output pin numbers. These devices perform the logic function for which they are programmed when they are in a circuit. If the digital circuit designer wants the device to perform a different logic function, it can be re-programmed.

These devices have titles such as PLDs (programmable logic devices), CPLDs (complex programmable logic devices), and FPGAs (field programmable gate arrays). These devices have different sizes and numbers of available input and output pins. The size of these devices, ranging from MOST GATES to FEWEST GATES, could be shown in the following order: 1) FPGAs, 2) CPLDs, and 3) PLDs.

Gate count is one of many variables we use to help us select the type of PLD we want to use in a digital circuit. A digital designer will be as, or more, concerned with PLD characteristics such as the total number of I/O (input/output) pins, switching speed (propagation delay), and the output's electrical characteristics (TTL, CMOS, and so on).

Digital circuit design, using programmable logic, uses various methods to generate the circuit. Designs can be entered in graphical form, meaning that you choose the type of gates that you would use and enter them in a logic diagram form. The typical way, however, to create a logic circuit for a programmable logic device is to use a programming language that allows you to enter the logic functions in a manner similar to Boolean algebra.

One thing to realize is that there is no fundamental difference in the design process when you are choosing between PLDs and fixed function logic devices. The difference is in the type of devices used to implement the design.

Various programming languages are used with programmable logic, but some of the more prevalent are VHDL, Verilog, and versions of the C programming language. The process for implementing a logic circuit design using HDL (hardware description language) may vary, but here are the steps that have to be followed:

  1. Write your HDL program or enter your logic circuit in gate form.
  2. Assign physical pin numbers and device type for programmable IC.
  3. Compile the program or graphic file with no errors.
  4. Simulate the circuit's behavior before downloading to the IC.
  5. If simulation is correct, download "file" to Programmable IC; if not, return to Step 1.

Test and verify that the device works as expected; if not, return to Step 1. An example of a VHDL program written to duplicate the majority tester circuit is shown below. Do not spend too much time trying to understand the coding; just notice the use of Boolean expressions to describe the circuit. We will study the use of VHDL for describing digital circuits in a later course.

-- HDL Design Example
--Topic 7

ENTITY majority IS

PORT ( A, B, C: IN BIT;
X: OUT BIT);

END majority;

ACHITECTURE design OF majority IS

BEGIN
X (A AND B) OR (A AND C) OR (B AND C);

END design;

Notice that the VHDL statement for Output X is an assignment statement (<=) with the relationships between INPUTS A, B, and C shown on the right-hand side of this statement in the form of a Boolean SOP expression. The only difference between this statement and its Boolean expression is that the words AND, OR, and NOT are used. This indicates the importance of understanding these terms and their logic functions, and shows us another way in which they are used. In this case, you are writing a program (software), in VHDL language that generates a hardware circuit when downloaded and implemented on a PLD.

 

Study Tools

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Flash Cards

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Practice Quiz

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1) How many NAND gates are required to create a two-input OR gate?

 

(Click to view Answer.)

2) Determine the Boolean expression for the circuit shown below.

 

This circuit is used for the practice quiz problem #2:

This circuit schematic shows four inputs, A, B, C and D, going into a two stage circuit build entirely of three two-input NAND gates. 

Stage 1: 

Inputs A and B are used as inputs for the First two-input NAND gate.  The output of this gate is the first input into the Stage 2 two-input NAND gate.

Inputs C and D are used as inputs for the Second two-input NAND gate.  The output of this gate is the second input into the Stage 2 two-input NAND gate.

Stage 2: 

The outputs for the A/B input two-input NAND gate and the C/D input two-input NAND gate are used as the inputs to the final two-input NAND gate.  The output for this two-input NAND gate is the output of the circuit and is marked with the label  “Y”

Image Description

 

(Click to view Answer.)

3) How many NAND gates are required to implement the Boolean expression ?

 

(Click to view Answer.)


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