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Arithmetic Circuits

Addition Rules | Unsigned and Signed Numbers | 2's Complement Representation of Negative Numbers | Unsigned Addition and Subtraction | Signed Addition and Subtraction | The Half-Adder Circuit | The Full-Adder Circuit | A Binary Adder | An Adder-Subtractor | Adders in VHDL

As discussed in the previous lectures, digital logic is binary in nature; every action performed by digital circuits depends on 0 and 1. Digital circuits perform all functions, including complex calculations, voice and video transmission and reception, and video and music recording, using just the values 0 and 1.

A key step in understanding how computers work is to study how we can perform arithmetic using just 0 and 1. We need to learn how computers perform their calculation, and we will examine how we can use basic digital circuits, just simple logic gates, to build a circuit to add and subtract numbers. We will use this basic circuit with some clever modifications in the next course to build a basic computer.

Addition Rules

In dealing with addition of binary numbers, there are only four rules.

These are simple to remember because they indicate in order that 0 + 0 is 0, 0 + 1 is 1, 1 + 1 is 2 (in binary), and 1 + 1 + 1 is 3 (in binary). Using these four rules, we can develop hardware capable of addition, subtraction, multiplication, and division for numbers of any size.

Unsigned and Signed Numbers

As you learned in ECET100, in digital systems there are only two states: 0 and 1. In building circuits to manipulate numbers in binary format, there is a limit to how many bits can be handled. In most computers, this limit is a factor of 8 so we see 8-bit, 16-bit, 32-bit, and 64-bit machines.

Consider the simplest example of an 8-bit machine. Because 2⁸ = 256, this means that 8 bits can represent the numbers from 0 through 255. In this example, all of the numbers are assumed to be positive. There are situations where we need both positive and negative numbers. The standard established for this case is to use the most significant bit (MSB) as a sign bit and the remaining seven bits to indicate the magnitude of the number.

By convention, the sign bit has been defined so that 0 indicates a positive number and 1 indicates a negative number. Using this system, there are still 256 possible values, but the range is +0 through +127 (0 is considered to be a positive number) and -1 through -128 for negative values. The number of positive and negative values is evenly divided.

2's Complement Representation of Negative Numbers

In ECET100, you saw that most digital systems use the 2's complement representation for negative numbers. The reason is simple. As we shall see, the 2's complement format allows hardware to subtract numbers by adding them. This is the major advantage of this formatting because the amount of hardware required is significantly reduced.

As a review, we create the 2's complement of any number by first 1's complementing the number (change all 1s to 0s and all 0s to 1s), and then adding 1 to the result.

Look at the 8-bit examples below. You can verify these conversions by using your calculator. If you put in a negative number and convert it to binary, your calculator will show you the number using the 2's complement representation.

Value	Binary	1's complement	2's complement	Value
1	00000001	11111110	11111111	-1
7	00000111	11111000	11111001	-7
21	00010101	11101010	11101011	-21
95	01011111	10100000	10100001	-95
128	10000000	01111111	10000000	-128

Unsigned Addition and Subtraction

Some examples of addition of 8-bit unsigned numbers are shown below. These examples use the four rules defined at the beginning of this lecture.

7 + 21:	0 0 0 0 1 1 1 x	<- Carry
7 =	0 0 0 0 0 1 1 1
21 =	0 0 0 1 0 1 0 1
28	0 0 0 1 1 1 0 0	<- Answer

Two additional examples are the following.

Notice what happens in the final example. We add 175 and 108 and get an answer of 27! The problem is that the answer, 283, is greater than 8 bits (remember, the largest 8-bit unsigned value is 255). This condition is indicated with an extra carry (shown in red) from the addition of the last two bits.

Now, let's see some examples of unsigned subtraction. Remember that we subtract by adding the 2's complement form of the number being subtracted.

Two additional examples are the following.

Again, notice what happens to the carry from the addition of the most significant bits. When there is a subtraction involving unsigned numbers, the final carry has a different meaning than in addition. In subtraction, the final carry indicates whether the answer is positive or negative. A 0 carry means the answer is negative, which is why (7 - 12) has an answer of 11111011; 2's complement for -5. A final carry of 1 indicates a positive answer.

One point of confusion is how we can have negative numbers when we are in an unsigned number system. The confusion arises because unsigned does not mean that we only have positive numbers; unsigned means that the MSB is not a sign bit and has position weight.

Signed Addition and Subtraction

Some examples of addition of 8-bit signed numbers are shown below. These examples still use the four rules defined at the beginning of this lecture.

7 + 21:	0 0 0 0 1 1 1 x	<- Carry
7 =	0 0 0 0 0 1 1 1
21 =	0 0 0 1 0 1 0 1
28	0 0 0 1 1 1 0 0	<- Answer

This example is identical to the example using unsigned numbers.

Although this example looks identical to the previous unsigned example, there is one significant difference. Because we are now using signed notation, we have added 93 to 108 and have an answer of -55. The problem is that the maximum positive value has been reduced to +127 and the answer exceeds that value. This situation, where two positive numbers are added and the answer is negative, is called overflow. This occurs when there are not enough bits available.

Here is an example using the same examples as before for signed subtraction.

This is identical to the unsigned case.

This is also identical to the unsigned number example, except in this case we do not have to examine the final carry bit to know that the answer is negative; the sign bit is sufficient.

The Half-Adder Circuit

In the example problems, you may have noted that there are two slightly different forms of additions being done: one involving three bits (the two numbers and the carry) and one involving only two bits (the two numbers in the least significant bit position only). Theoretically, we can build two different circuits for these cases. In practice, only the hardware for adding three bits is used. This is called a full adder. We will see why this is the case later in this lecture. For now, we examine the design and operation of the half adder, the circuit to add only two bits, because this circuit makes the full adder easier to understand.

As we have seen in earlier lectures, simple logic designs can be done by using truth tables to generate Boolean expressions. In the case of a half adder, there are only two inputs (representing the two single-bit numbers) and two outputs (the sum and the carry). For this case, there are only three rules: 0 + 0 = 00; 0 + 1 = 01; and 1 + 1 = 10. Translating this to a truth table gives the following.

A	B	S	C
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Table 3.1 Half-Adder Truth Table

From this table, the Boolean expressions can be found by noting that each HIGH output is a product term in a sum-of-products description. Thus,

The Full-Adder Circuit

The full adder is developed in a similar fashion as the half adder. In this case, there are three inputs (the two single-bit numbers and a carry from the previous operation) and the same two outputs. This case requires the final rule for addition, that 1 + 1 + 1 = 11. In truth table format:

Table 3.2 Full-Adder Truth Table

The truth table can be used to create Boolean equations, which can be simplified using either classical Boolean rules or by computer-aided methods, such as the Logic Converter tool available in Multisim. The result of the analysis and simplification is the following.

Rather than drawing this circuit in full schematic format, most references use a block diagram formulation as shown in Figure 3.1.

Figure 3.1: Full-Adder Block Diagram

A Binary Adder

By combining multiple full adders, we can create a circuit to add as many bits as we need. In Figure 3.2, four full adders are combined to create a circuit that will add two 4-bit numbers and give a 5-bit answer (four sum bits and a final carry out).

As an aside, we should note that adder circuits do not follow the general naming and orientation rules for logic schematics. The standard for logic schematics is for the circuit to be drawn from left to right, with inputs on the left and outputs on the right. In designating data, the standard is that the least significant bit be designated with an index of 0. As you can see, the circuit above does not follow these conventions. The reason is a historical holdover to show the numbers being added and the results with the least significant bit to the right and the most significant bit to the left. When we discuss other logic circuits in the following chapters, we will revert to left-to-right and 0 index for LSB conventions.

Let us take an example of adding two 4-bit numbers using this circuit. In Figure 3.4, we add 7 to 4 and get an answer of 11. (A = 7 = 0111; B = 4 = 0100; S = 11 = 1011)

Figure 3.2: Four-Bit Adder Example Operation

Try a few examples to verify that this works for any two 4-bit numbers.

An Adder-Subtractor

The 4-bit binary adder circuit can be utilized as an adder-subtractor by making use of the fact that adding the 2's complement of one number to another is equivalent to subtracting that number from the other number. In other words, 4 - 7 is the same as 4 + (-7), where the -7 is expressed in 2's complement format.

A circuit that implements the 2's complement method for subtraction is shown in Figure 3.3. Note the similarity to the conventional binary adder. The only modification is that the B-inputs are sent to the adder through exclusive-OR gates.

The truth table for the exclusive-OR gate used in this configuration is shown in Table 3.3.

Table 3.3 The Exclusive-OR Gate as Programmable Inverter

Figure 3.3: Four-Bit Adder/Subtractor

Here is how this circuit operates: When the switch is into logic 0 position, then the inputs to the adders are A and B, and the CIN for the least-significant full adder is logic 0. In this case, the circuit is functionally the same as the binary adder circuit discussed earlier.

When the switch is placed in the logic 1 position, then the inputs to the full adders are A and (NOT B), and the CIN for the least significant full adder is logic 1. This means that the inputs are A and the 1's complement of B. Because the least significant CIN is also a logic 1, that value is added to the sum of A and (NOT B), effectively creating the 2's complement of B. Hence, this circuit is subtracting B from A. As with the binary adder, a couple of examples demonstrate how this circuit operates.

	Binary Subtractor See how a 4-bit binary subtractor performs a subtraction operation.

Adders in VHDL

Adder design can be simplified by using INTEGER signal types in VHDL. Using the four-bit adder, we can represent each input and output as a single bit variable using BIT or STD_LOGIC types (A1, A2, …, B4), but this results in an awkward and time-consuming design process. If we represent each four-bit input as an INTEGER type with a (RANGE of 0 to 15) and do the same for the five-bit output (RANGE of 0 to 31), the design process simplifies as shown below.

Note that the COUT term as been integrated into the SOUT as the most significant bit.

Using the INTEGER signal type has two significant advantages over using BIT or SIGNAL-VECTOR types. First, the assignment operations are simplified from multiple Boolean expressions to a single, easy-to-understand equation. Second, the assignment operation is the same no matter what the size of the adder. For example, if we want to expand the adder to handle two 8-bit numbers, then the only changes required are in the ENTITY definitions for the sizes of AI, BI, and SOUT; the ARCHITECTURE never changes.