Print This Page|
|
Print This Page |
Overview | Control Circuits | Registers | Counter Overview | Ripple Counters | Synchronous Counters | Synchronous Counter Design Using VHDL | State Diagrams for Counters | Truncated Binary Counters | Truncated Binary Counters Design Using VHDL | Nonbinary Counters | Cascading Counters
| Overview |  |
Flip-flops find a wide variety of uses in digital circuits. The ability to store the occurrence of an external event allows for the development of circuits that can perform sequential actions based on the order in which the events occur. This is distinctly different from combinational logic in which the output is only dependent on the inputs.
In this lecture, we will explore two common uses for flip-flops: digital control circuits and counter. The discussion of the third common use, shift registers, is covered in next week’s lecture.
| Control Circuits | |
In Figure 5.1, the simple house alarm circuit from the last lecture has been redrawn using flip-flops instead of NAND latches.
The circuit shows inputs via three single-pole-double-throw switches, labeled Arm, Reset, and Door Closed. Each switch is wired with one throw connected to VCC and the other pole connected to ground. The output of the Arm switch is connected to the J input of a J-K flip-flop. The K input of that flip-flop is connected to ground. The Clear input of that flip-flop is connected to the output of the Reset switch. The Q output of the flip-flop is connected to a 2-input AND gate; the other input of that gate is connected to the output of the Door Closed switch. The output of the AND gate is connected to the J input of a second J-K flip-flop. The K input of the second flip-flop is connected to ground. The Clear input of this flip-flop is connected to the output of the Reset switch. The Q output of the second flip-flop is labeled Alarm. A clock source feeds the Clock input of both flip-flops.
 |
 |
 |
 |
|
|
View this simulation of an alarm flip-flop on a simple house alarm circuit. |
|
|||
 |
 |
|
||
As mentioned in the Week 4 Lecture, this circuit cannot be designed using combinational logic, because the system cannot work unless armed and needs to continue to drive the alarm even after the door is closed. The use of flip-flop instead of latch creates a more reliable circuit that is less prone to noise effects and is easier to troubleshoot. Note that the Arm switch has been replaced by a SPDT (single-pole double-throw) switch, because the flip-flop requires an active-HIGH input, and the NAND latch used an active-LOW input.
Let us now create a VHDL text file for the circuit in Figure 5.1.
The VHDL text file in Figure 5.2 has used a simple trick to simplify the Boolean descriptions. This involves using D flip-flop notation to create the same result as a J-K flip-flop. The method used creates a "hold-on" term that allows the D flip-flop to act in the same manner as a J-K device. This method is shown in Figure 5.3.
The figure shows how to create the equivalent of a J-K flip-flop using a D-type flip-flop. The equivalent circuit assumes that the J-K flip-flop has input A connected to the J input and input B connected to the K input. The equivalent D flip-flop circuit has its D input connected to the output of an OR gate. The inputs to this 2-input OR gate are the outputs from 2 AND gates. The input signals to the 2 input AND gate1 are InputA and the D flip-flop's not Q output. The input signals to the 2 input AND gate2 are Input notB and the D flip-flop's Q output.
The simplest method of determining the operation of a synchronous circuit is to draw a timing diagram. Try this for the circuits in Figure 5.3 and the circuit in Figure 5.1 to verify that the operation is as desired.
| Registers | |
A note about convention: In digital devices, data bits are numbered from the lowest to the highest in significance. The least significant bit (LSB) uses the "0" designation, and the most significant bit uses N-1 as a designator, where N is the number of bits. Therefore, in Figure 5.4, the LSB is labeled as D0 and the MSB as D3.
The VHDL representation of a register is straightforward. A simple text file for the 4-bit register from Figure 5.4 is shown in Figure 5.5.
The best examples of registers used in this way are some forms of solid state memory. In later classes, you will also see how registers can be used as temporary storage as part of arithmetic logic units, the computing portions of CPUs.
| Counter Overview | |
We now move to discussing how to utilize flip-flops to build binary counters. The concept of a modulus (MOD) will be discussed as a method for describing counters by specifying the number of unique counts produced before the count sequence repeats. The simplest counters are those with MOD numbers equal to 2N. There are many uses for these types of counters, as can be seen by examining many computer clock speeds. You will often find, particularly in older machines, that the clock speed is a 2N number to ease the hardware construction.
A common example of a MOD 2N counter can be found in standard clocks and watches. Today, most timekeeping devices are digitally driven with a crystal oscillator running at 32.768 kHz. The reason this value is chosen is because this is an inexpensive configuration for the oscillator and because the value is 1 Hz x 215. This means we need a 15-bit binary counter to produce a 1-second output.
The clock example points out the limitation of using 2N counters; namely that the number of seconds in a minute, minutes in an hour, and hours in a day are not 2N values. To be useful, we need, respectively, a MOD 60 counter to get minutes from seconds, a second MOD 60 counter to get hours from minutes, and a MOD 24 counter to get days from hours.
There is another class of digital counters that do not give sequential counts. There are some applications that require this type of counter. One example is a Gray code counter used in applications in which exact decodes of counting states are required. We will see an example of this counter later in this lecture.
Historically, the design of non-2N sequential counters has involved a great deal of work. This design technique is called classical and requires the use of many digital logic techniques. Fortunately, use of VHDL considerably simplifies this process. Before we explore counter design using VHDL, we need to discuss the use of state diagrams to define the counter operation.
| Ripple Counters | |
Consider a J-K flip-flop with both inputs tied to logic HIGH as shown in Figure 5.6. With this configuration, the flip-flop will toggle, as shown in Figure 5.7.
A timing diagram with two signals, Clock and Q. The Clock signal is a pulse train with a 50% duty cycle. The Q output changes state on the rising edge of each change in Clock. This results in a pulse train with 50% duty cycle at two times the period of Clock.
This is a timing diagram with four signals—Clock, Q0, Q1, and Q2. The Clock signal is a pulse train with a 50% duty cycle. There are nine Clock pulses shown. The Q0 output changes state on the rising edge of each change in Clock. This results in a pulse train with 50% duty cycle at two times the period of Clock. The Q1 output changes state on the rising edge of each change in Q0. This results in a pulse train with 50% duty cycle at two times the period of Q0 and four times the period of Clock. The Q2 output changes state on the rising edge of each change in Q1. This results in a pulse train with 50% duty cycle at two times the period of Q1 and eight times the period of Clock. The resultant states of the three flip-flop is shown at the bottom; a change occurs on each rising Clock edge. The states shown are 001, 010, 011, 100, 101, 110, 111, 000, and 001.
The circuit in Figure 5.8 is called a ripple counter, because each flip-flop serves as a clock for the next flip-flop; the initial clock ripples through the circuit. Because the counter has three flip-flops, this is known as a 3-bit counter. Also, a circuit with three flip-flops means that there are 23 = 8 possible states.
|
|
|
|
|
 3-Bit Binary Ripple Counter
Go through this tutorial that explains the output waveform of the 3-bit binary counter. This tutorial requires audio. |
|
|||
|
|
|||
In counters, the term MOD (for modulus) number is often used to designate the number of states allowed before the circuit begins to repeat itself. The circuit in Figure 5.8 is a MOD 8 counter. The MOD number of a counter determines how much frequency division occurs from the input clock to the final output. In general:
MOD # = Frequency in/Frequency out
Although ripple counters seem to work well in theory, there are severe limitations when using actual devices. The problem is with the various timing constraints discussed in the Week 4 Lecture. Remember that there are propagation delays from the clock edge to the flip-flop outputs (tPHL and tPLH) and a requirement for a setup time (tsu).
Figures 5.9 and 5.10 are Multisim simulations of the MOD 8 ripple counters at two different input clock frequencies. The first is at 10 kHz and the second is at 10 MHz. Notice that at the slower speeds, the circuit seems to operate correctly, but notice what happens at the higher frequency of 10 MHz.
This is a screen shot of an oscilloscope display for a 3-bit ripple counter. This display shows four signals, labeled Clock, Q0, Q1, and Q2, and is identical to the timing diagram shown in Figure 5.9 (described above).
This is a screen shot of an oscilloscope display for a 3-bit ripple counter. This shows a much higher clock rate, so that each of the flip-flop outputs is moved to the right to indicate propagation delays. This means that the changes of state for Q0, Q1, and Q2 no longer line up with the Clock signal or with each other. Because of these offsets, the count at 111 goes briefly to 110 and then briefly to 100 before settling to 000. After 000, the count goes to 001, and then briefly to 000, before settling to 010.
As you can see, the ripple counter does not produce a reliable count sequence at higher frequencies. As shown in the simulation, the counter increments from a count of 111 to a count of 000, but has transition counts of 110 and 100. In a similar fashion, the counter increments from 001 to 010 with a transition count of 000. These transition states at higher frequencies limit the use of ripple counters to applications running at relatively slow speeds, such as time-of-day clocks and watches.
| Synchronous Counters | |
The ripple counter is an example of using a synchronous device, the flip-flop, in an asynchronous application because there is not a common clock to all the flip-flops. A synchronous counter, with all flip-flops running off of the same clock, allows the design of counters that can operate at much higher clock frequencies than ripple counters. The design of a synchronous binary counter is based on the property of binary numbers during a count sequence. This property is illustrated in Table 6.1 for the binary count sequence from 0–7.
Image Description
|
Q2
|
Q1
|
Q0
|
|
0
|
0
|
0
|
|
0
|
0
|
1 (changes each time)
|
|
0
|
1 (change when Q0 = 1)
|
0 (changes each time)
|
|
0
|
1
|
1
|
|
1 (change when Q0 = Q1 = 1)
|
0 (change when Q0 = 1)
|
0
|
|
1
|
0
|
1
|
|
1
|
1
|
0
|
|
1
|
1
|
1
|
|
0 (change when Q0 =Q1 = 1)
|
0
|
0
|
From Table 5.1, we can generalize that when we count up in binary, any bit except the first bit will change states when all of the lower bits are HIGH. Using this algorithm, we can design the synchronous binary counter. A 3-bit binary up-counter is shown in Figure 5.11. This same technique can be expanded for any number of flip-flop stages.
Three J-K flip-flops are used with each using a common clock input. The NOT Q output of the flip-flop on the left is connected to the J input on that flip-flop, and the Q output is connected to the K input. That configuration causes the flip-flop to toggle and one-half the clock frequency. That configuration causes the middle flip-flop to toggle and one-half the frequency of the first flip-flop and one-fourth of the clock frequency. The Q outputs from the first flip-flop and middle flip-flop are ANDed together and connected to the J and K inputs of the right-hand flip-flop. That configuration causes the final flip-flop to toggle and one-half the frequency of the middle flip-flop and one-eighth of the clock frequency.
|
|
|
|
|
|
Go through this tutorial that explains the operation of a synchronous counter. This tutorial requires audio. |
|
|||
|
|
|||
| Synchronous Counter Design Using VHDL | |
Using Boolean equations to describe the circuit in Figure 5.11 is a challenge. An alternative solution is to use a series of IF_THEN_ELSE statements to describe the sequence of counter states. This approach is implemented as shown in Figure 5.12. Alternatively, this file could have been constructed using the CASE statement.
| Figure 5.12 — VHDL IF_THEN_ELSE Counter Description ENTITY counter3 IS PORT( CLK :IN BIT; Q :BUFFER BIT_VECTOR(2 downto 0)); END counter3; ARCHITECTURE behavior OF counter3 is BEGIN PROCESS(CLK) BEGIN IF (CLK'EVENT AND CLK = '1') THEN IF Q = "000" THEN Q <= "001"; ELSIF Q = "001" THEN Q <= "010"; ELSIF Q = "010" THEN Q <= "011"; ELSIF Q = "011" THEN Q <= "100"; ELSIF Q = "100" THEN Q <= "101"; ELSIF Q = "101" THEN Q <= "110"; ELSIF Q = "110" THEN Q <= "111"; ELSIF Q = "000"; END IF; END IF; END PROCESS; END behavior; |
One advantage of using the IF_THEN_ELSE approach is that an arbitrary count sequence can be specified. In this way, the VHDL compiler will determine the actual logic necessary to implement the counter, saving the designer the effort of conventional counter design. A variation of the IF_THEN_ELSE approach is to treat the counter as a finite state machine (FSM) and use VHDL techniques customized for design of these types of circuits. This approach is discussed later in this lecture. A third approach to counter design in VHDL makes use of the INTEGER type. This method is usually preferred in counter design because the resultant text design file is simple to construct and understand. An example of a design for the same 3-bit binary up-counter using this technique is shown in Figure 5.13.
|
Figure 5.13 — Counter Description Using INTEGER Types ENTITY counter3 IS |
The use of the INTEGER type has resulted in a one-line description of the counter operation. This same file works for any size binary up-counter; the only change necessary is to modify the range of the INTEGER values. For example, a 10-bit binary up-counter would be the same file with an INTEGER RANGE 0 TO 1023 used. Descriptions of counters may require the addition of control signals, such as presets, clears, and enables. These functions are handled in the same fashion as shown earlier for flip-flops. Figure 5.14 shows a 3-bit up-counter with an active-LOW asynchronous clear (CLR) and an active-HIGH synchronous enable to count signal (EBL).
|
Figure 5.14 — MOD-S Binary Up-Counter with Enable and Clear ENTITY counter8 IS |
The counter can be modified to produce a down counter (a binary counter that decrements instead of incrementing) by changing the ELSE statement to the following.
ELSE Q <= Q – 1;
| State Diagrams for Counters | |
State diagrams are used to graphically indicate the operation of a logic circuit. State diagrams are useful for designing logic circuits in which events occur in a fixed order. Circuits having this characteristic are known as finite state machines (FSMs). Counters are a special case of FSMs and are well suited to be described using state diagrams. A state diagram for a counter shows how the counts, or states, are related. Figure 5.15 is an example of a 3-bit binary up-counter.
This is a state diagram showing the eight states of a 3-bit binary up-counter. Each count state is represented by a circle with the value of a different count inside. Each circle feeds the other circle having the next sequential value: state 000 feeds state 001 feed state 010 feeds state 100 feeds state 101 feeds state 110 feeds state 111 feeds state 000 and so on.
In Figure 5.15, each bubble indicates one counter state. The arrows indicate the count progression; in this case, the count increments. The counter shown is a 2N type.
| Truncated Binary Counters | |
This is another state diagram. In this case, only five of the circles are interconnected, with state 000 feeding state 001 feeding state 010 feeding state 011 feeding state 100 feeding state 000 and so on. The three remaining states, 101, 110, and 111, all feed state 000.
Note that the unused states (counts 101, 110, and 111) feed the initial count (000). This is necessary so that if a counting error occurs, such as during power-on or in a noisy environment, the counter returns to the designed counting sequence. One traditional method of building this counter would be to design a MOD 8 binary up-counter and use the decode of count 101 to drive the RESET input of the three counter flip-flops. This means that the state 101 exists for a very small time, tens of nanoseconds, before resetting the counter back to 000.
A cleaner method for designing the MOD 5 counter is an approach that only has the five required states. This can be easily accomplished using VHDL.
| Truncated Binary Counters Design Using VHDL | |
|
Figure 5.17 — MOD-S Binary Up-Counter with Enable and Clear ENTITY counter5 IS
|
|
|
|
|
|
|
The VHDL text file in Figure 6.13 describes the desired operation of the counter. The VHDL compiler uses this file to create the actual hardware of the circuit. This simulation demonstrates the operation of this counter. |
|
|||
|
|
|
||
This form of a VHDL text file can be used to create any non-2N binary counter counting between any two states. To modify the circuit to handle a MOD 5 counter with values from 1 to 5 (instead of 0 to 4), we merely change the inner IF statement to the following.
IF Q = 5 THEN
Q <= 1;
| Nonbinary Counters | |
| Cascading Counters | |
Consider the arrangement shown in Figure 5.18. How is this designed? What is the output frequency?
There are two blocks shown, labeled MOD 5 Counter and MOD 10 Counter. The MOD 5 has a signal labeled fin input and outputs a signal labeled f1 to the MOD 10 Counter. The output of the MOD 10 Counter is labeled fout.
Begin with the timing diagram of the MOD 5 counter, shown in Figure 5.19.
This is a timing diagram with four signals—fin, Q0, Q1, and Q2. The Clock signal is a pulse train with a 50% duty cycle. There are seven pulses shown. The Q0 output changes state on the rising edge of each change in fin. This results in a pulse train with 50% duty cycle at two times the period of Clock. The Q1 output changes state on the rising edge of fin whenever Q0 is high. The Q2 output changes state on the rising edge of fin whenever both Q0 and Q1 are high. This is a standard binary output until the fifth pulse. At this point, the counter resets and the count begins from zero. The resultant states of the three flip-flop is shown at the bottom; a change occurs on each rising Clock edge. The states shown are 001, 010, 011, 100, 000, 001, and 010.
From the timing diagram, we can see that there are three frequencies available without having to use any decoding. As outputs, Q0 = fIN/2, Q1 = fIN/4, and Q2 = fIN/5. Because we have defined MOD number as (frequency in)/(frequency out), Q2 represents the final frequency output for this counter. Note that in a non-2N counter, the output does not have a 50% duty cycle; in this (f1)case, the duty cycle is 20%.
This shows us that in Figure 5.18, the Q2 would be the input clock to the MOD 10 counter. Because the MOD 10 counter divides its input frequency by 10,
fOUT = f1/10 = fIN/5/10 = fIN/50
Earlier in this lecture, the example of a time-of-day clock was used. Using that model, what are the MOD numbers for converting seconds into hours and seconds into days? How many flip-flops are required for the entire circuit?
Solving the first of these questions is a simple exercise in multiplication. Remember that the formula for MOD number can be restated as MOD # = (period out)/(period in), because frequency and period are simple reciprocals. Because seconds are converted into hours by passing through two cascaded MOD 60 counters, the period out = (60 sec/min)(60 min/hr) = 3600 sec; and the MOD # = (3600 sec)/(1 sec) = 3600.
For seconds into days, MOD # = 3600 x 24 = 86,400.
The total number of flip-flops required would be six for each of the MOD 60 counters (because 60 < 64 = 26) and five for the MOD 24 counter (since 24 < 32 = 25).
|
