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Overview | Shift Register Basics | Serial Versus Parallel Data Transmission | Shift Register Design Using VHDL | VHDL Concatenation and Variables | Shift Register Design Using VHDL Concatenation | Using VHDL to Implement Counter State Diagrams | Moore and Mealy Machines

Overview

This week’s lecture covers two different topics. First, we explore the third major use for flip-flops. Last week, we explored flip-flop usage in circuits creating registers and counters. The third primary use is in shift register.

For the second topic this week, we begin to examine the use of state diagrams in the design and development of sequential logic circuits to perform specific tasks. These types for circuits are known as state machines, because they can be viewed as executing consecutive logic operations depending on input conditions. State machines include all digital controllers and computers. We will begin by returning to last week’s material to see how VHDL can directly incorporate state diagrams into a counter design and then move into a general discussion on use of state diagrams. The material on state machine design will be concluded in next week’s lecture.

Shift Register Basics

Shift registers are a special class of registers that are connected so that bits can be moved between flip-flops in an ordered fashion. A simple example of what is called a serial-in parallel-out shift register is shown in Figure 6.1.

Figure 6.1: 4-Bit Serial-In Parallel-Out Shift Register

To understand how this circuit works, assume that the four flip-flops begin in a reset condition and that the Serial Data line inputs data at the Clock frequency (for each clock pulse, the data may be different). On the first clock, the first bit of Serial Data is loaded into Q0; on the second clock, the first bit of Serial data is shifted to Q1 and the second bit of Serial Data is loaded into Q0; and so on. After four clock pulses, four bits of Serial Data will have been loaded into the four flip-flops, and the Q0–Q3 output represents a parallel version of the serial input. This is illustrated in the simulation below.

The circuit in Figure 6.1 can be modified to reverse this process so that data is input in parallel and output in serial format. The circuit for this configuration is called parallel-in serial-out.

Serial Versus Parallel Data Transmission

A logical question at this point would be, "Why do we need to convert between parallel and serial data?" At first glance, many would assume that all data transfers should be parallel; sending multiple bits at once should be faster and simpler. In addition, computers operate on data in a parallel manner, as we will see in ECET330.

One obvious advantage of serial transmission is relative cost. Modern automobiles typically have over 100 microprocessors and hundreds of miles of wiring. The situation with modern aircraft is more dramatic with significantly more processors and thousands of miles of wiring. If each processor needs an average of 8 bits, then we have an 8-to-1 (technically 9-to-2  because we need ground wiring) weight advantage in using serial transmission. The weight savings alone make serial transmission more appealing, although there are additional savings in wiring material and labor costs.

Another obvious situation in which serial transmission is required is for conditions in which this is the only mode of transferring data. A telephone modem is one example, because the modem uses a single modulated signal. Another example is FM transmission, in which a single frequency is used.

A more surprising, counterintuitive reason for using serial transmission involves the transmission speed. At high speeds, parallel wires are susceptible to noise effects because of inductive coupling between the wires. As signals change states, they generate electromagnetic radiation that can be picked up by parallel wires. The longer the wires and the more parallel wires there are, the worse the condition. With serial transmission, there is no opportunity for signals to interfere with each other. Notice on your computer that the fastest peripherals connections are serial, such as Firewire and USB 2.0.

Let us consider a simplified version of a dial-up connection running at 56.6 kbaud (baud is a term used in serial transmission that, for our purposes, we define as bits/second). If we are sending data in an 8-bit (one-byte) format, this means that we are sending a new 8-bit packet every 141 µsec (8 bits divided by 56,600 bits per second). This is a simplification of an actual transmission scheme because commercial methods use additional bits to identify the beginning and end of each transmitted byte.

Figure 6.2 is a block diagram of our transmission scheme.

Figure 6.2: Simplified Dial-up Transmission Block Diagram

In this simplified scheme, a byte of data is parallel loaded into the first shift register every 141 µsec and shifted out and sent to the second shift register every 17.6 µsec. The second shift register assembles the serial data and is unloaded in parallel every 141 µsec.

Shift Register Design Using VHDL

Shift registers can be described easily in VHDL using the techniques already developed. A description of the 4-bit serial-in parallel-out shift register is shown in Figure 6.3. In this file, each bit of the shift register is defined individually. Although this works, imagine the amount of work necessary to describe a larger register with 16 or 32 bits.

An alternate, easier approach is to make use of a new feature: the concatenation operator.

VHDL Concatenation and Variables

The purpose of the concatenation operator, indicated by the ampersand symbol &, is to allow for the combination of bits so that there are an equal number of bits on both sides of the assignment operator, <=. A common use of the concatenation operator is to link together separate signals to treat them as a single entity.

In VHDL, a VARIABLE is a way to represent a temporary location for a group of logic values. Unlike the SIGNAL assignment, a VARIABLE assignment does not represent a physical wire in the system. The VARIABLE operator is often used to simplify the VHDL description of a circuit. When using a VARIABLE, a new assignment operator is used, the colon equal (:=). The VARIABLE operator is used within a PROCESS and does not exist outside of that PROCESS.

To demonstrate the use of the concatenation operators and VARIABLE assignment, consider the simple circuit shown in Figure 6.4. In this circuit, two of the inputs, E0 and E1, perform multiple functions. Each input is used individually to drive other circuits, and they are used together to select the outputs of a 2-to-4 decoder.

Figure 6.4: Logic Circuit With Multiple Uses of Enable Signal

Consider only the decoder portion of this circuit. Because E0 and E1 are used individually in different logic circuits, they cannot be defined as a vector. Using IF...THEN...ELSE descriptions, the 2-to-4 decoder can be defined as shown in Figure 6.5.

Compare this to the description shown in Figure 6.6

This seems like a lot of work just to simplify the enable bits, and it is. Remember that this is a trivial example designed to demonstrate the function of the VARIABLE assignment and concatenation operator. We only use these tools when required to simplify the description of a logic circuit.

Shift Register Design Using VHDL Concatenation

An example of the use of the concatenation operator is shown in the revised text file for the 4-bit serial-in parallel-out shift register in Figure 6.7.

The order of the register outputs on both sides of the assignment operator is critical. The assignment occurs from left to right so Q2 is assigned to Q3, Q1 to Q2, Q0 to Q1, and Serin to Q0.

Using VHDL to Implement Counter State Diagrams

Last week, we discussed implementation of counters using VHDL and the use of state diagrams to define a counter’s operation. Let’s look at one example from that lecture, the MOD 5 counter shown in Figure 6.8.

Figure 6.8: MOD 5 Binary Up-Counter State Diagram

VHDL can be used to directly implement state diagrams. To handle this form of description, the ARCHITECTURE section is specified to contain a new signal type. This is done using the TYPE statement. The TYPE statement defines a new signal type and the allowed values for that signal type. For example, we know that a BIT signal type has two values: 0 and 1. When we use the TYPE statement, we define the name of the new signal type and the values that type can have. User-defined types are called enumeration type. We use a new type to allow us to specify the description of the circuit using the states directly.

For the MOD 5 counter, the definition of the TYPE statement would look like this:

ARCHITECTURE fsm1 OF counter5 IS
TYPE STATE_TYPE IS (S7,S6,S5,S4,S3,S2,S1,S0);
SIGNAL state :STATE_TYPE;

The TYPE statement is used to define the eight identified states for this counter (S7–S0). The SIGNAL declaration is necessary because the values for the term “state” are not inputs to or outputs from the circuit. The STATE_TYPE notation identifies the form of the term “state”, which was specified in the TYPE statement. The combination of these two statements creates a SIGNAL named “state” with eight possible values, S7–S0.

The use of the VHDL state machine technique applied to the MOD 5 counter is shown in Figure 6.9. Once the “state” signal type is declared and assigned, a CASE statement is used to define the values for the counter. IF…THEN…ELSE statements are used to define how the counter progresses from its current state to its next state. The last section of the ARCHITECTURE uses a selected signal assignment to assign the state outputs to the required counter values.

At first glance, this seems to be more complicated than the IF...THEN...ELSE method demonstrated in last week’s lecture. This is true for this example, but the state machine technique proves easier to use for classes of finite state machines (FSMs).

Moore and Mealy Machines

Counters are a prime example of a state machine, sometimes called a finite state machine (FSM). A state machine is a synchronous circuit designed to implement a defined number of logic states in response to a clock or other input signals. In general, state machines follow one of two models, being classified as either Moore-type or Mealy-type.

A Moore state machine is a logic circuit in which there are no external controls affecting the output of the signal. Stated another way, the next state of a Moore machine depends only on the current state of the circuit when the clock occurs. Thus, the example of the MOD-5 counter shown above is an example of a Moore machine.

A block diagram for a Moore machine is shown in Figure 6.10.

Figure 6.10: Moore Type State Machine

Applying this diagram to the MOD-5 counter, the Memory section consists of the three flip-flops used, and the Control Circuit section contains the gates required to truncate the count so that the counter returns to a count of zero on the next clock after reaching a count of four. For this example, no Output Circuit section is required. Moore machines mainly include counters and shift registers, because the outputs are usually the result of the state of the flip-flops.

More complicated digital circuits involve controller functions in which the output of the circuit depends on both the state of the Memory section and control inputs. This generalized circuit is called a Mealy machine, as shown in Figure 6.11. Note the main difference from the Moore machine is that some of the Input signals are now used to affect the output. In a Mealy machine, the Output section is no longer optional, because this is where the Memory state is combined with the appropriate Input signals.

Figure 6.11: Mealy Type State Machine

Next week, we will explore the design and implementation of Mealy machines.