State Machine Design II

Overview | Review of Moore Machines | Moore Machines With Asynchronous Inputs | State Tables | Machines With Synchronous Inputs


Overview

For the topic this week, we continue examining the use of state diagrams in the design and development of sequential logic circuits to perform specific tasks. This week, we will focus on Mealy type state machines. We will begin by returning to last week’s material on Moore type state machines and contrast them with Mealy machines. We will then see how VHDL can directly incorporate state diagrams into a sequential system with both asynchronous and synchronous control.


Review of Moore Machines

The Moore type state machines covered last week change from one output condition to the next on every active clock edge. A Moore machine has a given number of possible states defined by the number of flip-flops in the system or the possible number conditions defined in VHDL. The two examples both had 8 states: one illustrated a truncated binary counter and the other illustrated a nontruncated binary counter. Either of these Moore machines could be modified to a Mealy machine by adding inputs. The behavior of this system would then be defined by the current output condition and the input’s condition.


Moore Machines With Asynchronous Inputs

The Moore state machine illustrated last week counting from 0–4 repetitively could be modified by adding an asynchronous input named RESET. The function of this signal would be to return the machine’s output to S0 whenever input RESET = ‘0’. This machine would always change to S0 when RESET = ‘0’ and no state change could occur until RESET = ‘1’. Every state change would then require RESET = ‘1’ and an active clock edge.

This circuit is illustrated in the state diagram shown in Figure 7.1. Note the difference is the inclusion of the RESET signal. In Figure 7.1, transitions between states only occur when RESET = “1” and State 0 is selected when RESET = “0”.

Figure 7.1: MOD-5 Counter With Asynchronous Reset

Image Description

Figure 7.1: MOD-5 Counter With Asynchronous Reset

A state diagram with five of the circles are interconnected. State 000 feeds state 001 feeds state 010 feeds state 011 feeds state 100 feeds state 000 and so on. The three remaining states, 101, 110, and 111, all feed state 000. The transitions between the five interconnected states are labeled with Reset = 1. State 000 has an additional input labeled Reset = 0.


State Tables

State machines can also be described with state tables. A state table allows the user to see the relationships between the required input and output conditions. The state table for the state machine described above is shown in Table 7.1.

RESET	Current State	Next State
0	S0 – S7	S0
1	S0	S1
1	S1	S2
1	S2	S3
1	S3	S4
1	S4	S5
1	S5	S6
1	S6	S7
1	S7	S0

Table 7.1: Current State-Next State Table

Table 7.1 illustrates a new terminology describing a state machine in reference to both the configuration of the circuit at a point in time and the configuration at the next point in time. This listing is referred to as a current state-next state table.

The VHDL program for this state machine is a modification of the MOD-5 state machine covered last week. The program for that design is repeated below in Figure 7.2.

**Figure 7.2: MOD 5 Binary Up-Counter Using State Types**
ENTITY counter3 IS PORT( CLK :IN BIT; Q :BUFFER BIT_VECTOR(2 downto 0)); END counter5; ARCHITECTURE fsm1 OF counter5 is TYPE STATE_TYPE IS(S7,S6,S5,S4,S3,S2,S1,S0); SIGNAL state :STATE_TYPE; BEGIN PROCESS(CLK BEGIN IF (CLK'EVENT AND CLK = '1') THEN CASE state IS WHEN S0 => state <= S1; WHEN S1 => state <= S2; WHEN S2 => state <= S3; WHEN S3 => state <= S4; WHEN S4 => state <= S0; WHEN OTHERS => state <= S0; END CASE; END IF; END PROCESS; WITH state SELECT Q <= "000" WHEN S0, "001" WHEN S1, "010" WHEN S2, "011" WHEN S3, "100" WHEN S4, "101" WHEN S5, "110" WHEN S6, "111" WHEN S7; END fsm1;

Editing this VHDL program to add the reset function requires us to define a new input called RESET in the ENTITY section defined as a BIT type. We also have to modify the program to be sure that anytime RESET = ‘0’, the output state will be S0. The modified program is shown in Figure 7.3.

**Figure 7.3: MOD 5 Binary Up-Counter With Asynchronous Inputs**
ENTITY counter5 IS PORT( RESET:IN BIT; CLK :IN BIT; Q :BUFFER BIT_VECTOR(2 downto 0)); END counter5; ARCHITECTURE fsm1 OF counter5 is TYPE STATE_TYPE IS(S7,S6,S5,S4,S3,S2,S1,S0); SIGNAL state :STATE_TYPE; BEGIN PROCESS(CLK BEGIN IF (CLK'EVENT AND CLK = '1') THEN CASE state IS WHEN S0 => state <= S1; WHEN S1 => state <= S2; WHEN S2 => state <= S3; WHEN S3 => state <= S4; WHEN S4 => state <= S0; WHEN OTHERS => state <= S0; END CASE; END IF; END PROCESS; WITH state SELECT Q <= "000" WHEN S0, "001" WHEN S1, "010" WHEN S2, "011" WHEN S3, "100" WHEN S4, "101" WHEN S5, "110" WHEN S6, "111" WHEN S7; END fsm1;


Machines With Synchronous Inputs

The state machine shown above is a simple example. More complex finite state machines will use multiple synchronous inputs to determine their operation. Before progressing, we need to refine how we construct state diagrams. Figure 7.4 is a diagram showing a standard notation used for a finite state machine.

Figure 7.4: State Diagram Notation

(From “Digital Design with CPLD Applications and VHDL” by Robert Dueck, Thompson Delmar Learning, 2005)

Image Description

Figure 7.4: State Diagram Notation

A state diagram with two bubbles. The top bubble is labeled with the word start separated by a horizontal line from the number 0. A call-out identifies the word start as the state name, and another call-out identifies the number 0 as the state variable. The bottom bubble is labeled with the word continue separated by a horizontal line from the number 1. The top bubble has a line at the top leaving and returning after an arc. This line is labeled with a 1 followed by a slash, followed by 00. Another line connects the top bubble to the bottom bubble on the right-hand side. This line has an arrowhead at the bottom bubble and is labeled 0 slash 10. A call-out identifies the 0 as the input value; another call-out identifies the 10 as the output value. The right-hand connection is labeled as a conditional transition. On the left-hand side is a line connecting the bottom bubble back to the top bubble. There is an arrowhead at the top bubble. This line is labeled with X slash 01 and identified as an unconditional transition.

The diagram uses a simple case of a system with two state variables labeled 0 and 1. Another way to think of this is that our circuit has four possible configurations because 2² = 4 (the configurations are 00, 01, 10, and 11). For convenience, the two variable are given names; in this case start and continue. The lines connecting the two states identify both the input condition required for a change of state and the resulting output configuration. All of the transitions are synchronous.

Let’s look at the initial state labeled “start.” The diagram shows that as long as the input value is “1,” the circuit remains in the state with both outputs at Q = 0 (hence the circuit configuration is 00). When the input becomes a 0, on the next clock the circuit changes to the continue state. This transition results in a change in the outputs so that one continues to have Q = 0, but the other changes to Q = 1 (the circuit configuration becomes 10). On the next clock edge, the circuit changes again, because the required value for the input is an X, indicating the transition occurs independent of the value for that variable. The outputs both toggle (giving a configuration of 01). The circuit has now returned to the starting configuration and either changes to 00 if the input is 1, or to 10 if the input is 0.

Interestingly, this diagram can be implemented as either a Moore or Mealy type machine. The difference is that in a Moore machine, the outputs will be synchronous; in the Mealy machine, only one of the outputs needs to be synchronous. The actual implementation depends on the characteristics of the inputs and the requirements for the outputs.

Let’s apply this notation to the state diagram used in the elevator controller from Lab 6. The original diagram is shown in Figure 7.5.

Figure 7.5: Elevator State Diagram From Lab 6

Image Description

Figure 7.5: Elevator State Diagram From Lab 6

This is a state diagram with six states. The state bubbles are labeled as S0 through S5. The S0 bubble is identified with the conditions doors open, direction down, and motion stopped. The S0 bubble is connected to the S1 bubble with both an input and an output line. The output line is labeled floor 1 or call 1; the input line is labeled d open or call 2. The S1 bubble is identified with the conditions doors closed, direction down, and motion stopped. The S1 bubble is connected to the S2 bubble with an output line. The output line is labeled floor 1 or call 1. The S2 bubble is identified with the conditions doors closed, direction down, and motion moving. The S2 bubble is connected to the S3 bubble with an output line. The output line is labeled arrived 1. The S3 bubble is identified with the conditions doors open, direction up, and motion stopped. The S3 bubble is connected to the S4 bubble with an input and an output line. The output line is labeled floor 2 or call 2; the input line is labeled d open or call 1. The S4 bubble is identified with the conditions doors closed, direction up, and motion stopped. The S4 bubble is connected to the S5 bubble with an output line. The output line is labeled floor 2 or call 2. The S5 bubble is identified with the conditions doors closed, direction up, and motion moving. The S5 bubble is connected to the S0 bubble with an output line. The output line is labeled arrived 2.

This system has four inputs.

Floor 1 Call (0 = no call, 1 = call from Floor 1 button or elevator Floor 1 select
Floor 2 Call (0 = no call, 1 = call from Floor 2 button or elevator Floor 2 select
Door Open/Closed (0 = open, 1 = closed)
Floor (0 = Floor 1, 1 = Floor 2)

There are four output states required.

Door Control (0 = open, 1 = closed)
Elevator Direction (0 = down, 1 = up)
Motion (0 = stopped, 1 = moving)

Using the notation from Figure 7.4, Figure 7.5 can be redrawn as shown in Figure 7.6.

Figure 7.6: Elevator State Diagram Using Standard Notation

Image Description

Figure 7.6: Elevator State Diagram Using Standard Notation

A state diagram with six states. The state bubbles are labeled as S0 through S5. The S0 bubble is identified with the name wait2. The S0 bubble is connected to the S1 bubble with both an input and an output line. The output line is labeled 0X01/100; the input line is X111/000. The S1 bubble is identified with the name close2. The S1 bubble is connected to the S2 bubble with an output line. The output line is labeled 1011/101. The S2 bubble is identified with the name move21. The S2 bubble is connected to the S3 bubble with an output line. The output line is labeled XXX0/010. The S3 bubble is identified with the name wait1. The S3 bubble is connected to the S4 bubble with an input and an output line. The output line is labeled X100/110; the input line is labeled 1X10/010. The S4 bubble is identified with the name close1. The S4 bubble is connected to the S5 bubble with an output line. The output line is labeled 0110/111. The S5 bubble is identified with the name move21. The S5 bubble is connected to the S0 bubble with an output line. The output line is labeled XXX1/000. Both the S0 and S3 bubbles have addition output/input loops. The loop for S0 is labeled 0X01/000; the loop for S3 is labeled X001/010.

The advantage of the diagram shown in Figure 7.6 is the ease in translating directly into VHDL coding. Using classical digital design techniques is much more labor intensive, requiring translation of the state diagram into a current-state, next-state diagram (similar to Table 7.1, but expanded to include all input combination), followed by translation into Boolean equations and simplification. Using VHDL greatly simplifies this process.